Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. To further enhance transistor performance, MOSFET devices have been fabricated using strained channel regions located in portions of a semiconductor substrate. Strained channel regions allow enhanced carrier mobility to be realized, thereby resulting in increased performance when used for n-channel (NMOSFET) or for p-channel (PMOSFET) devices. Generally, it is desirable to induce a tensile strain in the n-channel of an NMOSFET transistor in the source-to-drain direction to increase electron mobility and to induce a compressive strain in the p-channel of a PMOSFET transistor in the source-to-drain direction to increase hole mobility. There are several existing approaches for introducing strain in the transistor channel region.
In one approach, strain in the channel is introduced by forming a stress layer, such as silicon germanium, over a silicon substrate. The difference in the lattice structure between the silicon substrate and the overlying silicon germanium creates a stress layer, thereby creating stress in the channel region of a subsequently formed transistor.
In this approach, a silicon capping layer is frequently formed over the silicon germanium to prevent the formation of germanium oxide and to aid in the formation of a gate oxide. The process of forming the silicon capping layer, however, is difficult to control. Furthermore, a silicon germanium oxide may nonetheless form during the process of forming the gate oxide. The silicon germanium oxide often exhibits a high interface state density (Dit) and bulk traps, thereby decreasing the performance of the transistor.
Accordingly, there is need for a method to induce strain in the channel region such that the performance characteristics of transistors are enhanced.